The present invention regards a CMOS switch circuit for transferring high voltages. In particular, the present invention refers to the final stage of the row or column decoder of a nonvolatile memory wherein cells are read at a higher voltage than the supply voltage (boosted read voltage).
As is known, the need to have available nonvolatile memories with increasingly higher densities leads to the use of multilevel memories, where the information, stored in floating-gate regions of the cells, is coded through a number of logic levels, thus fractionating the quantity of charge stored in each cell.
FIG. 1 shows the characteristic that links the gate-to-source voltage Vgs to the drain-to-source current Ids of a flash cell for a two-level memory, i.e., wherein information is coded in each memory cell via a bit having two possible values, associated, respectively to an on condition of the cell and to an off condition of the cell, which in turn depends upon a programmed or not programmed state of the cell. In particular, in FIG. 1, Vtv and Vtw represent the value of the gate-to-source voltage Vgs at which a flash cell starts conducting current, in the case of a virgin (erased) cell and of a written cell, respectively. In a memory of this type, logic value xe2x80x9c1xe2x80x9d is generally associated to the characteristic having threshold voltage Vtv normally comprised between 0.5 and 2.5 V, and the logic value xe2x80x9c0xe2x80x9d is associated to the characteristic having threshold voltage Vtw generally higher than 5 V.
It is moreover known that reading a memory cell comprises converting the current absorbed by the memory cell, at a given gate-to-source voltage Vgs, into a voltage which is then translated to an output CMOS level.
In case of multilevel cells, the plane (Vgs, Ids) is divided by a number of characteristics (as shown, for example, in FIG. 2, which regards storing two bits per cell) corresponding to four logic values xe2x80x9c11xe2x80x9d, xe2x80x9c10xe2x80x9d, xe2x80x9c01xe2x80x9d, and xe2x80x9c00xe2x80x9d. In this case, the four logic values correspond to four different threshold values Vt1, Vt2, Vt3, and Vt4, which in turn are linked to different quantities of charge stored in the floating gate regions of the memory cells.
Cell programming is affected by uncertainty, and the characteristics both of FIG. 1 and of FIG. 2 represent the central values of the actually obtainable distributions. In practice, each threshold value is associated to a respective distribution of values comprised between a minimum value and a maximum value set apart from the maximum value of the previous distribution and/or from the minimum value of the subsequent distribution in a way sufficient for enabling correct reading of the cells. In addition, each distribution may present a different amplitude, as shown, for example, in FIG. 3, which shows the distributions associated to memory cells, each storing two bits, and in which the scale is not uniform.
Also in this case, reading comprises converting the current flowing in a cell into a voltage. The thus obtained voltage is then compared with different voltage values that are intermediate between the threshold distributions referred to above.
One of the problems that arise when reading multilevel cells is linked to the read voltage applied to the gate terminals of the cells to be read. In fact, at the selected read voltage, all the read cells (with the possible exception of the cells programmed at the highest threshold value) must be on, so as to allow the converted voltage to be compared with the different voltage levels. Consequently, the read voltage must be at least higher than the last threshold voltage but one (Vt3 in FIG. 2; VR in FIG. 3, here 6 V).
Such a high read voltage is particularly problematic to handle in devices that have a single supply voltage VCC, the nominal value of which is typically 3 V. In fact, high voltages are generated inside the nonvolatile memory by means of particular devices referred to as boosters or charge pumps. The Thevenin equivalent circuit of a charge pump 10 usable for this purpose is shown in FIG. 4 and comprises an ideal voltage source 11 generating a voltage V1 and an equivalent resistor 12 connected in series to the ideal voltage source 11. The equivalent resistor 12 is further connected to a load 13 represented as a current source. FIG. 5 shows the output characteristic of the charge pump 10. As may be noted, the output voltage V0 of the charge pump 10 is maximum when load 13 does not absorb current, and reduces linearly as the current absorbed by the load 13 increases.
In particular, from FIG. 5 it may be deduced that, when an output voltage not lower than Vp is desired, the load 13 cannot absorb a current higher than Ipmax. Usually, charge pumps integrated in CMOS technology manage to supply currents smaller than 1 mA. Word lines being read require 6 V, with a maximum ripple of 50 mV. For this reason, the output of the charge pump is connected to a voltage regulator which, being supplied by the voltage of the charge pump 10, is able to yield a constant voltage of adequate value. It is evident that, in order to maintain the 6 V read voltage on the gate terminal of the cell to be read with adequate precision, it is necessary to consume as little current as possible during cell addressing.
The cell addressing phase, which determines switching of the row driving circuit, supplied at a 6-V read voltage, however, creates some problems. In fact, the switching control signals have a high logic level equal to the supply voltage, which, in the worst case, may be 2.5 V, so that there exists the problem of getting voltages with very different values to coexist in one and the same driving circuit, as will be explained in detail hereinafter.
The row decoder may be schematically represented by a number of inverters (one per row) controlled by a combinational circuit receiving the input addresses and having the function of driving the inverters in such a way that, each time, only one of them will have a high output. In particular, this combinational circuit sends a low logic signal to the inverter connected to the selected row (so that it will present a high output) and a high logic signal to all the other inverters. In this regard, see FIG. 6, showing one of the driving inverters 21, comprising a pull-up PMOS transistor 22 and a pull-down NMOS transistor 23, having coupled gate terminals (input node 24), coupled drain terminals (output node 25), and source terminals connected, respectively, to a first supply line 26 set at VPP and to a ground line.
The described simplified scheme works correctly when VPP=VCC, but does not work in the case described above, when the read voltage VPP is generated by a charge pump. In fact, in the latter case, the combinational circuit supplies, as a high logic level on input node 24 of the inverters of the non-selected rows, the read voltage VCC, whilst the first supply line 26 is set at the voltage VPP greater than VCC. In this situation, between the gate and the source terminals of the pull-up transistors 22 of the driving inverters 21 of the non-selected rows, there is a non-zero voltage drop. If this voltage reaches the value of the threshold voltage of the transistors 22, the latter switches on, and the output node 25 of the inverters does not succeed in reaching a zero voltage value, as, instead, would be necessary to guarantee correctness of reading.
To solve the above problem, a first solution, shown in FIG. 7, involves the use of a positive feedback inverter using a feedback transistor 27 of PMOS type, connected between a first supply line 26 and the input node 24 of the driving inverter 21, and having a gate terminal connected to the output node 25. FIG. 7 moreover shows a NAND gate 30 belonging to the row selection combinational circuit and supplied at the read voltage VCC via a second supply line 31.
In this case, when the voltage on the output node 25 decreases, the feedback transistor 27 switches on and couples the input node 24 to voltage VPP on the first supply line 26, guaranteeing complete switching off of the pull-up transistor 22 and zeroing of the output voltage.
Also this solution is, however, not free from drawbacks, the main one of which being represented by the fact that the source-bulk junction of the PMOS transistors of the NAND gate 30 is directly biased and may give rise to current losses, given that these transistors have the source region biased at VCC and the drain region (connected to the output) and the bulk region biased at VPP. To solve the above problem, it is possible to insert an NMOS-type pass transistor or a CMOS pass switch for separating the low-voltage part (predecoding) from the high-voltage part (decoding).
This solution is shown in FIG. 8, wherein the NAND gate 30 drives the driving inverter 21 through an NMOS pass transistor 32 having the gate terminal biased at VCC.
In the solution of FIG. 8, when the output of the NAND gate 30 is high (VCC), the pass transistor 32 operates as a diode, since it has two terminals (gate terminal and terminal connected to the output of the NAND gate 30) set at the same voltage; consequently, it generates a voltage drop between the output of the NAND gate 30 and the node 24 which is equal to its own threshold voltage.
As a consequence, also the solution illustrated in FIG. 8, besides entailing further circuit complications, is not optimal in the case of low supply voltage in that, in this condition, the voltage drop on the pass transistor 32 is such as not to enable the node 24 to reach the high voltage necessary for switching off completely the pull-up transistors 22, and thus the levels of consumption are high.
On the other hand, the use of a CMOS pass only shifts the problem of undesiredly biasing other parts of the circuit, besides entailing an unacceptable encumbrance for the decoding, made in the pitch of the array row.
In addition, the circuit of FIG. 8 has a high current consumption during switching, which is particularly burdensome for read voltages VPP of the order of 6 V, which are required for reading multilevel cells, as discussed above, and is slow during switching, which further aggravates the problem of consumption referred to above.
The aim of the present invention is therefore to provide a switch circuit that is able to transfer a high voltage to a load or circuit downstream, with reduced consumption during switching, in the presence of an input signal at a lower voltage.
According to the present invention, a switch circuit is provided, as definedin claim 1.
In practice, the switch circuit comprises a first inverter stage and a second inverter stage (feedback branch and driving branch, respectively) connected to the boosted supply line. The first inverter stage (feedback branch) has the top transistor (first main PMOS transistor) feedback-controlled, and the bottom transistor) controlled by the input signal, while the second inverter stage is controlled by the first inverter via an intermediate node. A first switching (from a deselected state to a selected state of the output) is activated directly by the input signal, while a second switching (from the selected state to the deselected state of the output) is activated via an activation element which raises the intermediate node or lowers the output. In this way, no components have two different terminals receiving the two supply voltages VCC and VPP, and thus the problems presented by known circuits are solved.